以及技巧先进性,现在Freescale PowerPC


e500 core MPC8572,MIPS性能高达6897,ARM我看频率是1G的都没有,ARM
大概是 1.1 MIPS/MHz,Power Architecture


相信将来用的人会愈来愈多 四是,价格方面,总有人抱怨说PowerPC处




PowerPC  Memory Management Model (MMU)
The MMU specifications are largely provided by the OEA. The primary
functions of the MMU are to
translate logical (effective) addresses to physical addresses for memory
accesses and I/O accesses (most
I/O accesses are assumed to be memory-mapped), and to provide access
protection on a block or page
basis. Note that many aspects of memory management are
implementation-dependent. The description in
Chapter 7, “Memory Management,” describes the conceptual model of a MMU;
however, processors may
differ in the specific hardware used to implement the MMU model.
Processors require address translation for two types of
transactions—instruction accesses and data
accesses to memory (typically generated by load and store
The memory management specification includes models for 32-bit
implementations. The MMU of a 32-bit
processor provides 232 bytes of logical address space accessible to
supervisor and user programs with a
4-Kbyte page size and 256-Mbyte segment size.
In 32-bit implementations, the entire 4-Gbyte memory space is defined by
sixteen 256-Mbyte segments.
Segments are configured through the 16 segment registers.
The block address translation (BAT) mechanism maps large blocks of
memory. Block sizes range from
128 Kbytes to 256 Mbytes and are software-selectable. In addition, the
MMU of 32-bit processors uses an
interim virtual address (52 bits) and hashed page tables in the
generation of 32-bit physical addresses.
Two types of processor-generated accesses require address translation:
instruction accesses and data
accesses to memory generated by load and store instructions. The address
translation mechanism is
defined in terms of segment tables (or segment registers in 32-bit
implementations) and page tables used
to locate the logical-to-physical address mapping for instruction and
data accesses. The segment
information translates the logical address to an interim virtual
address, and the page table information
translates the virtual address to a physical address.
Translation lookaside buffers (TLBs) are commonly implemented to keep
recently-used page table entries
on-chip. Although their exact characteristics are not specified by the
architecture, the general concepts that
are pertinent to the system software are described.
The block address translation (BAT) mechanism is a software-controlled
array that stores the available
block address translations on chip. BAT array entries are implemented as
pairs of BAT registers that are
accessible as supervisor SPRs; refer to Chapter 7, “Memory Management,”
for more information.




PowerPC  Interrupt Model
The interrupt mechanism, defined by the OEA, allows the processor to
change to supervisor state as a
result of external signals, errors, or unusual conditions arising in the
execution of instructions. When
interrupts occur, information about the state of the processor is saved
to various registers and the processor
begins execution at an address (interrupt vector) predetermined for each
type of interrupt. Interrupt handler
routines begin execution in supervisor mode. The interrupt model is
described in detail in Chapter 6,
“Interrupts.” Note also that some aspects regarding interrupt conditions
are defined at other levels of the
architecture. For example, floating-point exception conditions are
defined by the UISA, whereas the
interrupt mechanism is defined by the OEA.
The architecture requires that interrupts be handled in program order
(excluding the optional floating-point
imprecise modes and the reset and machine check interrupt); therefore,
although a particular
implementation may recognize interrupt conditions out of order, they are
handled strictly in order. When
an instruction-caused interrupt is recognized, any unexecuted
instructions that appear earlier in the
instruction stream, including any that have not yet begun to execute,
are required to complete before the
interrupt is taken. Any interrupts caused by those instructions must be
handled first. Likewise, interrupts
that are asynchronous and precise are recognized when they occur, but
are not handled until all instructions
currently executing successfully complete processing and report their
The OEA supports four types of interrupts:
? Synchronous, precise
? Synchronous, imprecise
? Asynchronous, maskable
? Asynchronous, nonmaskable